/* 
cpu：80~90
sdram ：125Mhz 比较脆弱，需要多次尝试才行
-150 小瑕疵
-155 ok
-160 ok
-165 瑕疵

sdram：100Mhz,-135

*/
 
module top(
  input clk_50M,
  input key2,
  output led,
  
  //uart接口
  input uart_rxd,
  output uart_txd,

  //input cy_SCL,
  output cy_rst_out,
  inout [15:0] cyData,
  output cy_IFCLK_out                     ,
  input cy_to_fpga_CTL0_FLAGA        ,
  input cy_to_fpga_CTL2_FLAGC        ,
  input cy_to_fpga_CTL1_FLAGB        ,
  input cy_to_fpga_A7_FLAGD          ,
  output  cy_from_fpga_RDY1_SLWR       ,//output
  output  cy_from_fpga_RDY0_SLRD       ,//output
  input cy_A0_INT0                   ,
  output cy_A1_INT1                   ,
  output  cy_from_fpga_A2_SLOE         ,//output
  input cy_A3_WU2                    ,
  //output  cy_from_fpga_A4_FIFOADR0     ,//output
  output  cy_from_fpga_A5_FIFOADR1     ,//output
  //output  cy_from_fpga_A6_PKTEND       ,//output

  output w25q64_ncs,
  output w25q64_clk,
  inout w25q64_di_io0,
  inout w25q64_do_io1,
  inout w25q64_nwp_io2,
  inout w25q64_nhold_io3,
  
  //SDRAM 芯片接口
  output        sdram_clk_out,                //SDRAM 芯片时钟
  output        sdram_cke,                //SDRAM 时钟有效
  output        sdram_cs0_n,               //SDRAM 片选
  output        sdram_cs1_n,               //SDRAM 片选
  output        sdram_ras_n,              //SDRAM 行有效
  output        sdram_cas_n,              //SDRAM 列有效
  output        sdram_we_n,               //SDRAM 写有效
  output [ 1:0] sdram_ba,                 //SDRAM Bank地址
  output [12:0] sdram_addr,               //SDRAM 行/列地址
  inout  [15:0] sdram_data,               //SDRAM 数据
  output [ 1:0] sdram_dqm,                //SDRAM 数据掩码

  input hid_dat_n,
  input hid_clk_n,
  input hid_str_n,

  output audio_pwm,

  inout [7:0] ch375_d,
  input ch375_int,
  output ch375_a0,
  output ch375_cs,
  output ch375_rd,
  output ch375_wr,

  //sdcard
  input   spi_MISO,        //     spi.MISO
  output  spi_MOSI,        //        .MOSI
  output  spi_SCLK,        //        .SCLK
  output  spi_CS,         //        .SS_n
 
  input flash_data0,
  output flash_sdo,
  output flash_sce,
  output flash_dclk,

  output ds1302_clk,
  inout  ds1302_dat,
  output ds1302_rst,
  
  output led_data_read,
  output led_data_write,
  //output led_ins_read,
  input hid_debug_uart_in,

  //VGA接口                          
  output          vga_hs,         //行同步信号
  output          vga_vs,         //场同步信号
  output  [15:0]  vga_rgb,         //红绿蓝三原色输出 

  input dummy
);

wire sys_rst_n;
assign sys_rst_n = key2 && locked_sdram && locked_cpu && locked_vga;
assign spirom_nwp_io2 = 1'b1;
assign spirom_nhold_io3 = 1'b1;

assign myuart_rxd = uart_rxd;
//assign uart_txd = myuart_txd;
assign uart_txd = myuart_txd && hid_debug_uart_in;

reg [31:0] cnt;
reg flg;
always @(posedge clk_cpu or negedge sys_rst_n) begin
  if (!sys_rst_n) begin
    cnt <= 0;
	 flg <= 0;
  end else begin
    cnt <= cnt+1'b1;
	 if(cnt==32'd50000000)begin
		cnt <= 0;
		flg <= ~flg;
	 end
  end
end


wire vga_clk_25M;
wire vga_clk_65M;
wire sdram_clk;
wire clk_cpu = clk_cpu1;
wire locked_vga;
wire locked_sdram;
wire locked_cpu;
//例化PLL, 产生各模块所需要的时钟
pll_clk u_pll_sdram(
  .areset	(~key2),
  .inclk0             (clk_50M),
  .c0                 (sdram_clk),
  .c1                 (sdram_clk_out),//-75deg
  .locked             (locked_sdram)
);
 
//例化PLL, 产生各模块所需要的时钟
pll_vga u_pll_vga(
  .inclk0             (clk_50M),
  .c0                 (vga_clk_25M),
  .c1                 (vga_clk_65M),
  .locked             (locked_vga)
);

wire clk_cpu1;
wire clk_cpu2;
//例化PLL, 产生各模块所需要的时钟
pll_cpu u_pll_cpu(
  .areset	(~key2),
  .inclk0             (clk_50M),
  .c0                 (clk_cpu1),
  //.c1                 (clk_cpu2),
	.locked             (locked_cpu)
);
// wire cpu_clk_sel;
// lpm_mux	LPM_MUX_component (
// 			.data ({clk_cpu2, clk_cpu1}),
// 			.sel (cpu_clk_sel),
// 			.result (clk_cpu)
// 			);
// defparam
// 	LPM_MUX_component.lpm_size = 2,
// 	LPM_MUX_component.lpm_type = "LPM_MUX",
// 	LPM_MUX_component.lpm_width = 1,
// 	LPM_MUX_component.lpm_widths = 1;
// //myaltclkctrl myaltclkctrl_ins (
// //.clkselect(cpu_clk_sel),
// //.inclk0x(clk_cpu1),
// //.inclk1x(clk_cpu2),
// //.outclk(clk_cpu)
// //);

//25Mhz
assign cy_IFCLK_out = vga_clk_25M;
wire   cy_IFCLK_in  = ~vga_clk_25M;
 
 
wire hid_dat = ~hid_dat_n;
wire hid_clk = ~hid_clk_n;
wire hid_str = ~hid_str_n;
wire video_de;
wire [15:0] vga_rgb_ori;

assign vga_rgb = video_de ? vga_rgb_ori : 16'h0;


system 
#(
  .H_SYNC(11'd136), //行同步
  .H_BACK(11'd160), //行显示后沿
  .H_DISP(11'd1024),//行有效数据
  .H_TOTAL(11'd1344),  //行扫描周期 
  .V_SYNC(11'd6),  //场同步
  .V_BACK(11'd29),  //场显示后沿
  .V_DISP(11'd768),  //场有效数据
  .V_TOTAL(11'd806),  //场扫描周期
  .EXTRA_UP(11'd0),
  .EXTRA_DOWN(11'd0),
  .SPI_QUARD(0)
)system_inst(
  .clk      (clk_cpu),        //     clk_cpu
	.clk_50M  (clk_50M),
  .sdram_clk(sdram_clk),
  .sdram_clk_trans(sdram_clk),
  .video_clk (vga_clk_65M),
  .reset_n  (sys_rst_n),  //   reset.reset_n

  .sdram_cke     (sdram_cke     ),   //        .ba
  .sdram_cs0_n   (sdram_cs0_n    ),   //        .cas_n
  .sdram_cs1_n   (sdram_cs1_n    ),   //        .cas_n
  .sdram_ras_n   (sdram_ras_n   ),   //        .cke
  .sdram_cas_n   (sdram_cas_n   ),   //        .cs_n
  .sdram_we_n    (sdram_we_n    ),   //        .dq
  .sdram_ba      (sdram_ba      ),   //        .dqm
  .sdram_addr    (sdram_addr    ),   //        .ras_n
  .sdram_data    (sdram_data    ),   //        .we_n
  .sdram_dqm     (sdram_dqm     ),

  .myuart_rxd     (myuart_rxd),     //  myuart.rxd
  .myuart_txd     (myuart_txd),      //        .txd

  .hid_clk   (hid_clk ),
  .hid_dat   (hid_dat ),
  .hid_str   (hid_str ),

  //sdcard
  .softspi_MISO        (spi_MISO),        //     spi.MISO
  .softspi_MOSI        (spi_MOSI),        //        .MOSI
  .softspi_SCLK        (spi_SCLK),        //        .SCLK
  .softspi_CS          (spi_CS),         //        .SS_n    
  

  .cyData(cyData),
  .cy_rst_out(cy_rst_out),
  //.cy_SDA(cy_SDA)       ,
  .cy_IFCLK(cy_IFCLK_in),
  .cy_to_fpga_CTL0_FLAGA(cy_to_fpga_CTL0_FLAGA),
  .cy_to_fpga_CTL2_FLAGC(cy_to_fpga_CTL2_FLAGC),
  .cy_to_fpga_CTL1_FLAGB(cy_to_fpga_CTL1_FLAGB),
  .cy_to_fpga_A7_FLAGD(cy_to_fpga_A7_FLAGD),
  .cy_from_fpga_RDY1_SLWR(cy_from_fpga_RDY1_SLWR)       ,//output
  .cy_from_fpga_RDY0_SLRD(cy_from_fpga_RDY0_SLRD)       ,//output
  .cy_from_fpga_A2_SLOE(cy_from_fpga_A2_SLOE)         ,//output
  .cy_A0_INT0(cy_A0_INT0)                   ,
  .cy_A1_INT1(cy_A1_INT1)                   ,
  .cy_A3_WU2(cy_A3_WU2)                    ,
  //.cy_from_fpga_A4_FIFOADR0(cy_from_fpga_A4_FIFOADR0)     ,//output
  .cy_from_fpga_A5_FIFOADR1(cy_from_fpga_A5_FIFOADR1)     ,//output
  //.cy_from_fpga_A6_PKTEND(cy_from_fpga_A6_PKTEND)       ,//output

  .audio_pwm (audio_pwm),
  
  .ch375_d      (ch375_d  ),
  .ch375_int    (ch375_int),
  .ch375_a0     (ch375_a0 ),
  .ch375_cs_out (ch375_cs ),
  .ch375_rd     (ch375_rd ),
  .ch375_wr     (ch375_wr ),


  //.w25q64_ncs       (w25q64_ncs      ),
  //.w25q64_do_io1    (w25q64_do_io1   ),
  //.w25q64_nwp_io2   (w25q64_nwp_io2  ),
  //.w25q64_nhold_io3 (w25q64_nhold_io3),
  //.w25q64_clk       (w25q64_clk      ),
  //.w25q64_di_io0    (w25q64_di_io0   ),

  //.w25q64_ncs       (w25q64_ncs      ),
  //.w25q64_clk       (w25q64_clk      ),
  //.w25q64_di_io0    (w25q64_di_io0   ),
  //.w25q64_do_io1    (w25q64_do_io1   ),

  .w25q64_ncs       (flash_sce      ),
  .w25q64_clk       (flash_dclk      ),
  .w25q64_di_io0    (flash_sdo   ),
  .w25q64_do_io1    (flash_data0   ),

  .ds1302_clk       (ds1302_clk),
  .ds1302_dat       (ds1302_dat),
  .ds1302_rst       (ds1302_rst),
  
  .led_data_read         (led_data_read),
  .led_data_write        (led_data_write),
  .led_ins_read          (led_ins_read),

    .video_hs       (vga_hs),
    .video_vs       (vga_vs),
    .video_de       (video_de),
    .video_rgb      (vga_rgb_ori),

  .cpu_clk_sel (cpu_clk_sel),
  
  .dummy(dummy)
  
 );


endmodule
            

  